Most of the recent display systems are respectively provided with a frame buffer comprising a plurality of memory planes so that a plurality of bits correspond to one pixel to retain information such as colors, concentrations, etc. There exists a system for manipulating such information in the frame buffer, called the BitBlt. The raster operations which can be performed in the BitBlt system have been defined as the Boolean operations between sources and destinations or between sources, destinations and additionally provided third rectangular areas called patterns or masks. The details of the BitBlt system are described in "Smalltalk-80 The Language and its Implementation," Addison-Wesley, 1983, A. Goldberg and D. Robson, chapter 18. Further, U.S. Pat. No. 3,976,982 discloses an image processing system for performing logical operations of images.
Briefly speaking, the BitBlt is a function of designating a rectangular area in a frame buffer by bits and transferring it to another display area. In its transfer, logical operations such as AND, OR, XOR, etc. are performed on the contents stored in the source and the destination. Therefore, the word is often used synonymously with raster operations. When raster operations are performed in a frame buffer comprising a plurality of memory planes, it is usual to employ a single raster operation circuit in common to all of the planes or to provide a separate raster operation circuit to each of the planes.
In the conventional raster operation circuits, the logical operations have been limited only to each of the memory planes, whether a single raster operation circuit is provided in common to all of them or a separate raster operation circuit is provided to each of them. For example, if a frame buffer is assumed to comprise four memory planes and a source and a destination are denoted with Si (i=0, 1, 2, and 3) and Di, respectively, the conventional raster operation circuits could perform operations such as Di.rarw.f (Si, Di) (f is a given logical function), but could not easily perform operations including interplane operations such as shown below. EQU D0.rarw.S0.multidot.S1.multidot.D3 EQU D1.rarw.S2+D2 EQU D2.rarw.(S3+D2).multidot.S0 EQU D3.rarw.D3
The Japanese Patent Unexamined Published Application No. 55-79,486 discloses a display device employing an inter-layer operation circuitry which performs interplane or inter-layer operations. The inter-layer operation circuitry, comprising a plurality of separate logical circuits, is provided between a frame buffer or a refresh memory and a TV monitor. The circuitry has no function to write the operation results back to the refresh memory, and therefore, cannot perform such complex logical operations as mentioned above.